• Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
    NVIDIA (09/12/24)
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  • Senior Timing Methodology

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
    NVIDIA (10/26/24)
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  • SRAM Timing Engineer

    NVIDIA (Santa Clara, CA)
    …power NVIDIA's next generation of AI chips. What you will be doing: + Drive robust methodology for timing analysis of custom circuit IP. + Support SRAM and ... the world! We are currently looking for a SRAM Timing Engineer to join our team of...other custom circuit design engineers through successful timing convergence towards tape-out. + Work closely with design… more
    NVIDIA (10/22/24)
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  • ASIC Engineer , Physical Design

    Meta (Sunnyvale, CA)
    …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design implementation ... logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology… more
    Meta (10/22/24)
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  • Digital Mixed Signal Design Engineer

    Meta (Sunnyvale, CA)
    …Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop cutting-edge AMS ... optimize state-of-the-art AMS IP's, while also supporting the development of next-gen custom mixed signal IC's for our industry-leading virtual and augmented reality… more
    Meta (10/03/24)
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  • CAD Engineer - TPG

    Micron Technology, Inc. (Atlanta, GA)
    …tools and flows for the design, implementation, verification, & tape out of custom memory designs! These CAD tools & collateral enable DRAM, NAND, and other ... software and system development within the highly specialized domain of custom IC design and implementation. **Responsibilities** **:** + Perform day-to-day support… more
    Micron Technology, Inc. (09/20/24)
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  • Senior Logic Design Engineer

    Microsoft Corporation (Austin, TX)
    …produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer ... We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence...Crossing (CDC), Reset Domain Crossing (RDC), power etc. + Timing closure of high-performance digital Intellectual Property (IP) +… more
    Microsoft Corporation (11/08/24)
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  • Sr. Silicon ATE Engineer , Project Kuiper

    Amazon (Sunnyvale, CA)
    …an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of ... the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design… more
    Amazon (08/16/24)
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  • SPF/Spice CAD Engineer - TPG

    Micron Technology, Inc. (Richardson, TX)
    …tools and flows for the design, implementation, verification, & tape out of custom memory designs! These CAD tools and collateral enable DRAM, NAND, and other ... teams. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells,… more
    Micron Technology, Inc. (10/25/24)
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  • Sr. Staff Design Engineer (Low Power)

    Qualcomm (Santa Clara, CA)
    …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more
    Qualcomm (10/10/24)
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