- NVIDIA (Santa Clara, CA)
- Are you looking for a SOC Design Engineer opportunity? If yes, come and join us. The complexity of the chip has greatly increased over the years. We are now ... group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and… more
- Amazon (San Diego, CA)
- …AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr . SOC Design Engineer -STA to continue to innovate on behalf of ... Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC . - Streamlining the timing signoff criterions, timing analysis...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. -… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC /ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... of enabling human life on Mars. SR . SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON...weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a Senior Design Engineer to design , analyze, and evolve next generation SoC solutions. We are looking for special individuals with ... cases. + Collaborate with Architects, Chip Leads, and Customers on SOC IP design , development, timing closure, power analysis, methodology alignment, and program… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …annually using our products. The CSG Central Applications Engineering team seeks an experienced SoC design engineer to integrate and support Cadence IP ... to make an impact on the world of technology. Senior Principal Design Engineer -...IP integration. + Develop examples and best practices for SoC system design , verification, and testbenches for… more
- SpaceX (Irvine, CA)
- Sr . SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... of enabling human life on Mars. SR . SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- Skyworks (San Jose, CA)
- Sr . Principal Analog Design Engineer Apply now " Date:Aug 25, 2024 Location: San Jose, CA, US Company: Skyworks If you are looking for a challenging and ... individuals who together are changing the way the world communicates. Requisition ID: 72766 Sr . Principal Analog Design Engineer Are you looking for the… more
- SpaceX (Redmond, WA)
- Sr . DDR IP Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. SR . DDR IP DESIGN ENGINEER ...support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $160,000.00 - $220,000.00/per… more
- L3Harris (Camden, NJ)
- Job Title: Sr ASIC/FPGA VHDL Design Engineer Job Code: 12189 Job Location: Camden, NJ (relocation can be provided for those that qualify) Schedule: 9/80 ... Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part...Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for… more
- Amazon (Boise, ID)
- …tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior RTL Design Engineer , you will be part of an advanced architecture team ... for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing...in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,… more