• Sr . RTL Design

    Amazon (Boise, ID)
    …Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior RTL Design Engineer , you will be part of an advanced architecture team ... with team members across multiple disciplines - Develop detailed design specifications and documentation - Perform RTL ...detailed design specifications and documentation - Perform RTL coding and synthesis - Work with Partners/Supplier to… more
    Amazon (09/11/24)
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  • Sr ASIC Modem design Engineer

    Amazon (Redmond, WA)
    …communities around the world. Come work at Amazon! We're hiring a Sr . Modem Engineer within a high performance ASIC design team. This team is using industry ... in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level...models in MATLAB. - Involve in control plane logic design and interfaces to bus fabrics. - Explore and… more
    Amazon (09/03/24)
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  • Senior Software Engineer

    NVIDIA (Santa Clara, CA)
    design process + Develop and enhance C++ based software tools to improve RTL design productivity and quality + Research and develop software solutions to ... rtl , and gate level designs. As a software engineer , you will craft highly efficient software to automate...stand out from the crowd: + Good architecture and RTL design knowledge + Strong expertise in… more
    NVIDIA (07/07/24)
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  • SerDes RTL Senior Principal Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and ... and developing flows at all phases of the digital design and functional verification. It is further expected that...well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate… more
    Cadence Design Systems, Inc. (07/06/24)
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  • Senior Mixed-Signal Intellectual Property…

    Microsoft Corporation (Redmond, WA)
    …are looking for ** Senior Mixed-Signal Intellectual Property Register Transfer Level (IP RTL ) Design Engineer ** who look for customer focused solutions, ... for a ** Senior ** **Mixed-Signal Intellectual Property Register Transfer Level (IP RTL ) Design Engineer ** to join the team. **Microsoft's mission is to… more
    Microsoft Corporation (09/21/24)
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  • Senior RTL Analysis Methodology…

    NVIDIA (Santa Clara, CA)
    …make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and supports ... of proven experience with tools and methodologies for ASIC design and verification. + Direct experience with RTL... design and verification. + Direct experience with RTL Linting EDA tools. + Proficiency in Verilog and… more
    NVIDIA (06/24/24)
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  • Hardware Engineering Manager - RTL

    BAE Systems (Manchester, NH)
    …based on position level and/or job specifics. **Hardware Engineering Manager - RTL Design Verification (Hybrid)** **105415BR** EEO Career Site Equal Opportunity ... time split between working onsite and remotely. BAE Systems is seeking a Design Verification Manager to work within our Electronic Systems business area leading a… more
    BAE Systems (09/11/24)
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  • Sr . DDR IP Design Engineer

    SpaceX (Redmond, WA)
    Sr . DDR IP Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. SR . DDR IP DESIGN ENGINEER ...support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $160,000.00 - $220,000.00/per… more
    SpaceX (07/22/24)
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  • Sr ASIC/FPGA VHDL Design

    L3Harris (Camden, NJ)
    Job Title: Sr ASIC/FPGA VHDL Design Engineer Job Code: 12189 Job Location: Camden, NJ (relocation can be provided for those that qualify) Schedule: 9/80 ... Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part...from system requirements and developing detailed architecture + Execute design ( RTL AND/OR HLS (C++ to … more
    L3Harris (06/27/24)
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  • Sr . SOC/ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    Sr . SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... this possible, with the ultimate goal of enabling human life on Mars. SR . SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At… more
    SpaceX (08/24/24)
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