• Senior Clocks Methodology

    NVIDIA (Santa Clara, CA)
    …us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order ... has increased significantly. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What… more
    NVIDIA (08/09/24)
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  • Senior DFX Methodology

    NVIDIA (Santa Clara, CA)
    We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... memory BIST, scan and array dump and DFX security methodology . + In addition, you will help develop and...Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we… more
    NVIDIA (07/12/24)
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  • Senior DFD Methodology

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior DFT Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of ... mechanisms which include scan dump, array dump, and JTAG methodology . + Develop and deploy DFD methodologies and tools...Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we… more
    NVIDIA (08/28/24)
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  • Senior DFT Methodology

    NVIDIA (Santa Clara, CA)
    …imagination and intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works on groundbreaking innovations involving crafting creative ... + Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power. + Experience in...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (08/28/24)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and/or full chip level. + Work with PD, DFX, Clocks , and other teams in coming up with timing...experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS… more
    NVIDIA (09/20/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design-for-Test Engineering ... for the most complex chips in the world, from methodology , to deployment to post-silicon lifecycle support. + Partner...+ Good exposure to multiple domains including RTL & clocks design, STA, place-n-route and power, to ensure we… more
    NVIDIA (09/14/24)
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  • Senior Engineer - Core Platform Test

    Qualcomm (San Diego, CA)
    …test team responsible for technologies including USB, PMIC, PCIe, Hypervisor, Boot, Clocks and Storage. Role will involve balancing some hands-on testing and ... Quality, ARM architecture, Linux, RTOS programming. + Strong understanding of test methodology . + Good understanding of the software development cycle. + Proven… more
    Qualcomm (09/03/24)
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  • Senior DFX Architect

    NVIDIA (Santa Clara, CA)
    …products, you will participate to drive major aspects of DFX architecture and methodology that will enable NVIDIA GPUs, custom processors and accelerators to excel ... + Good exposure in multi-functional areas including RTL, DFT, clocks , performance and power. + Excellent analytical skills in...are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
    NVIDIA (08/24/24)
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