- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- Micron Technology, Inc. (Dallas, TX)
- …the design and development of HBM base die SoC solutions, including top - level design , verification, and integration of various IP blocks. + Ensure ... signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate- level design... top talent to build a world-class HBM SoC design team. + Challenge the team… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for an SOC Design Engineer opportunity? If yes,...sophisticated GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Google (Sunnyvale, CA)
- …performance, efficiency, and integration. In this role, you will join a team working on SoC - level RTL design for our data center accelerators. You'll own ... instantiation, customization and generation of RTL. + Experience with SOC implementation standards and interfaces (eg AXI). + Experience...top - level RTL, architecture, design , and implementation of… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- Capgemini (San Francisco, CA)
- … convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verification. . 15 years' experience ... with SoC design (Digital design and development RTL) . Experience with chiplet architecture and partitioning for SiP packages. . Experience with various bus… more
- SpaceX (Irvine, CA)
- …STA Signoff. + Experience with power intent and upf development for block and soc top . + Familiar with formal verification and implementing functional ecos. + ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- The Boeing Company (Huntington Beach, CA)
- …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC/FPGA/ SoC design and verification - eg Synopsys VCS, Design ... Xilinx Vivado; and Universal Verification Methodology (UVM) + Experience working on large-scale SoC design teams. + Experience developing digital ASICs and SoCs… more
- Meta (Sunnyvale, CA)
- …the ML accelerator. 2. Define and track detailed internal integration test plans for top - level design components, and SOC vendor test plans and use case ... and/or C/C++ based verification. 11. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 12.… more