• Machine Learning ASIC Engineer

    Meta (Sunnyvale, CA)
    **Summary:** Meta is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. Our servers and data centers are the foundation upon ... engineers to build "Green" data center accelerators. **Required Skills:** Machine Learning ASIC Engineer , Architecture Responsibilities: 1. Work on… more
    Meta (08/31/24)
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  • ASIC Engineer , Architecture

    Meta (Sunnyvale, CA)
    …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Architecture Responsibilities: 1. Work with AI/ML experts in ... on hardware accelerators, develop functional and performance models of the architecture and conduct extensive functional and performance analysis using these models.… more
    Meta (09/14/24)
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  • ASIC Engineer , Architecture

    Meta (Austin, TX)
    …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Architecture Responsibilities: 1. Work with AI/ML experts in ... on hardware accelerators, develop functional and performance models of the architecture and conduct extensive functional and performance analysis using these models.… more
    Meta (07/18/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...System Verilog 11. Experience in one of these skills: Micro- architecture and RTL development for complex control and data… more
    Meta (07/19/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...equivalent practical experience. 7. 10+ years of experience in micro- architecture and RTL development for complex control and data… more
    Meta (09/06/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Qualifications:** Minimum Qualifications: 7. 15+ years of experience in micro- architecture and RTL development for complex control and data… more
    Meta (07/19/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro- architecture development ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Experience in one of these skills (minimum 3 years): Micro- architecture and RTL development for complex control and data… more
    Meta (07/20/24)
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  • ASIC Engineer , Performance…

    Meta (Sunnyvale, CA)
    …and IP for data center applications. **Required Skills:** ASIC Engineer , Performance Architect Responsibilities: 1. Performance Architecture and Modeling for ... **Summary:** Meta is hiring Performance Architect ASIC Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine… more
    Meta (07/19/24)
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  • ASIC Engineer - Infra Silicon…

    Meta (Menlo Park, CA)
    …the entire Silicon Lifecycle to build and scale silicon for data center applications.As an ASIC Engineer in the Infra Silicon Enablement team team, you will be ... innovative ASIC solutions for Meta's data center applications. **Required Skills:** ASIC Engineer - Infra Silicon Enablement Responsibilities: 1. Work across… more
    Meta (09/20/24)
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  • Senior Principal Front End ASIC Design…

    BAE Systems (San Jose, CA)
    …a senior level chip designer who has strong proficiency in both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout ... based on position level and/or job specifics. **Senior Principal Front End ASIC Design Engineer (Hybrid)** **105684BR** EEO Career Site Equal Opportunity… more
    BAE Systems (09/18/24)
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